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US Patent 12027416 BEOL etch stop layer without capacitance penalty

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
September 16, 2021
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Date of Patent
July 2, 2024
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Patent Application Number
17476521
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Patent Citations
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US Patent 8089135 Back-end-of-line wiring structures with integrated passive elements and design structures for a radiofrequency integrated circuit
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US Patent 8450212 Method of reducing critical dimension process bias differences between narrow and wide damascene wires
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US Patent 8669181 Diffusion barrier and etch stop films
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US Patent 8815743 Through substrate via semiconductor components and methods of formation thereof
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US Patent 8907458 Creation of vias and trenches with different depths
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US Patent 10453700 Low damage low-k dielectric etch
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US Patent 9520395 FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack
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US Patent 10629480 Method for forming semiconductor device structure
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US Patent 7442637 Method for processing IC designs for different metal BEOL processes
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US Patent 7443029 Adhesion of copper and etch stop layer for copper alloy
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Patent Inventor Names
Chih-Chao Yang
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Chanro Park
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Kenneth Chun Kuen Cheng
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Koichi Motoyama
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12027416
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Patent Primary Examiner
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Thanhha S. Pham
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CPC Code
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H01L 21/76829
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H01L 21/76832
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H01L 21/76834
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H01L 21/76846
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H01L 21/76816
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H01L 23/5329
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H01L 23/535
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H01L 23/5283
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H01L 23/528
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H01L 23/525
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