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US Patent 12068554 Dual-path high-speed interconnect PCB layout solution

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
0
Date Filed
January 28, 2022
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Date of Patent
August 20, 2024
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Patent Application Number
17587818
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Patent Citations
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US Patent 7305509 Method and apparatus for zero stub serial termination capacitor of resistor mounting option in an information handling system
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US Patent 7361981 Pad layout
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US Patent 7441222 Differential pair connection arrangement, and method and computer program product for making same
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US Patent 9433083 Edge mount connector arrangement with improved characteristic impedance
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US Patent 7453338 Impedance-matching electrical connection apparatus for high-speed data communications system
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US Patent 11093426 USB recepticle configuration and system therefor
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US Patent 6985365 Topology for flexible and precise signal timing adjustment
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US Patent 7159203 Differential delay-line
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Patent Inventor Names
Paul Danna
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Chi Kim Sides
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Vincent W. Michna
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12068554
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Patent Primary Examiner
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Vanessa Girardi
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CPC Code
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H05K 3/3405
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H01R 12/716
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