US Patent 12072378 Debug state machine triggered extended performance monitor counter

An integrated circuit (IC) includes a debug controller, a debug state machine (DSM), and an extended performance monitor counter (EPMC). The debug controller that selectively outputs debug data on a debug interconnect. The DSM identifies an event based on the debug data and an event list and outputs a DSM indication that identifies the event. The EPMC indicates a plurality of detected events including the identified event. The EPMC indicates the identified event in response to the DSM indication.