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US Patent 12087623 Dielectric liners on through glass vias
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Patent
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Date Filed
January 25, 2024
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Date of Patent
September 10, 2024
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Patent Application Number
18422346
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Patent Citations
US Patent 8148263 Methods for forming conductive vias in semiconductor device components
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US Patent 8155292 Telephone system and server apparatus
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US Patent 9596768 Substrate with conductive vias
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US Patent 9478504 Microelectronic assemblies with cavities, and methods of fabrication
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US Patent 11282777 Semiconductor package and method of manufacturing the same
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US Patent 7256146 Method of forming a ceramic diffusion barrier layer
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US Patent 7964965 Forming thick metal interconnect structures for integrated circuits
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Patent Inventor Names
M Ziaul Karim
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Christopher Lane
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Ramakanth Alapati
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
12087623
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Patent Primary Examiner
David A Zarneke
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CPC Code
H01L 21/76843
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H01L 21/486
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H01L 21/481
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H01L 23/15
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H01L 23/5384
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H01L 23/5329
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H01L 23/5226
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H01L 23/49827
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H01L 23/49822
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H01L 2224/05087
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