US Patent 12087772 Nanosheet device architecture for cell-height scaling

A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.