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US Patent 12093618 Automated circuit generation

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
May 8, 2023
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Date of Patent
September 17, 2024
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Patent Application Number
18314007
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Patent Citations
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US Patent 8001494 Table-based DFM for accurate post-layout analysis
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US Patent 10699051 Method and system for performing cross-validation for model-based layout recommendations
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US Patent 10770160 Programmable resistive memory formed by bit slices from a standard cell library
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US Patent 10783292 Automated analog layout
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US Patent 10783296 Matched net and device analysis based on parasitics
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US Patent 10796059 Integrated circuit layout generation method and system
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US Patent 10808333 Method and apparatus for performing layout designs using stem cells
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US Patent 10846456 Integrated circuit modeling methods and systems
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US Patent 10885258 Fixing ESD path resistance errors in circuit design layout
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US Patent 11243687 User terminal apparatus and controlling method thereof
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•••
Patent Inventor Names
John Mason
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Karen Mason
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Calum MacRae
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12093618
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Patent Primary Examiner
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Phallaka Kik
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CPC Code
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G06F 30/347
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G06F 30/373
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G06F 30/31
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G06F 30/38
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G06F 2111/12
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G06F 30/398
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G06F 30/367
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G06F 30/392
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G06F 30/327
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