US Patent 12112805 Apparatus containing memory array structures having multiple sub-blocks

Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a plurality of sets of field-effect transistors with each of the sets of field-effect transistors between the data line and a respective string of series-connected memory cells and having N field-effect transistors that are fabricated to have a respective binary permutation of two threshold voltages of a plurality of possible binary permutations of two threshold voltages having N positions, and N select lines that are each connected to a control gate of a respective field-effect transistor of each of the sets of field-effect transistors.