Is a
Patent attributes
Patent Applicant
0
Patent Jurisdiction
Patent Number
Patent Inventor Names
Shigeru Kawanaka0
Date of Patent
May 24, 2005
0Patent Application Number
104005660
Date Filed
March 28, 2003
0Patent Citations Received
Patent Primary Examiner
Patent abstract
A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.