Patent attributes
A highly economical alterable ASIC contains multiple fully optimized custom ASIC designs in one IC foot-print, each design utilizing the entire IC. The user can switch between multiple independently stored optimized logic applications instantly. The alterable ASIC comprises programmable logic blocks and user configurable circuits. Either random access memory (RAM) configuration circuits or mask configured read only memory (ROM) configuration circuits are stacked in separate module layers above a single logic module layer. Each RAM or ROM layer implements one design application and global control signals provide user selection. Alterable ASIC dissever the effective die cost, requires one smaller package, occupies one site on the PC board and needs less board level wires. An extremely low cost solution for system designs is realized with an alterable ASIC.
