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US Patent 7064579 Alterable application specific integrated circuit (ASIC)

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
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Date Filed
June 22, 2004
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Date of Patent
June 20, 2006
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Patent Application Number
10872594
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Patent Citations Received
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US Patent 12136562 3D semiconductor device and structure with single-crystal layers
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US Patent 12094965 3D semiconductor device and structure with metal layers and memory cells
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US Patent 12094892 3D micro display device and structure
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US Patent 12120880 3D semiconductor device and structure with logic and memory
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US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells
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US Patent 11854857 Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
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US Patent 11855100 Multilevel semiconductor device and structure with oxide bonding
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US Patent 11855114 Multilevel semiconductor device and structure with image sensors and wafer bonding
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US Patent 11862503 Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
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US Patent 11869591 3D memory devices and structures with control circuits
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•••
Patent Inventor Names
Raminda Udaya Madurawe
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
7064579
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Patent Primary Examiner
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Nathan J. Flynn
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