Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Jiong-Ping Lu0
Date of Patent
August 29, 2006
Patent Application Number
10734768
Date Filed
December 12, 2003
Patent Primary Examiner
Patent abstract
A capping layer (118) is used during an anneal to form fully silicided NiSi gate electrodes (120). The capping layer (118) comprises a material with an affinity for boron, such as TiN. The capping layer (118) serves as a boron trap that reduces the interface boron concentration for PMOS transistors without reducing the interface arsenic concentration for NMOS transistors.
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