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US Patent 7124221 Low latency multi-level communication interface
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Patent
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Date Filed
January 6, 2000
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Date of Patent
October 17, 2006
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Patent Application Number
09478916
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Patent Citations Received
US Patent 11971820 Variable modulation scheme for memory device access or operation
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US Patent 11750359 Low power edge and data sampling
US Patent 11775460 Communicating data with stacked memory dies
US Patent 11789879 Memory device supporting a high-efficient input/output interface and a memory system including the memory device
US Patent 11909568 Techniques for communicating multi-level signals
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Patent Inventor Names
Bruno W. Garlepp
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Jared L. Zerbe
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Kevin S. Donnelly
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Mark A. Horowitz
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Pak S. Chau
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Stefanos Sidiropoulos
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Billy W. Garrett, Jr.
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Carl W. Werner
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
7124221
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Patent Primary Examiner
Tim Vo
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