Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Atsushi Suwa0
Katsushi Tara0
Tadayoshi Nakatsuka0
Date of Patent
February 6, 2007
0Patent Application Number
108643510
Date Filed
June 10, 2004
0Patent Citations Received
Patent Primary Examiner
Patent abstract
Four switching circuit sections consisting of four FETs connected in series are provided between a plurality of input/output terminals which output and input a high frequency signal. Gate control voltages are individually applied to gate terminals of four FETs, respectively, so that an on-state and an off-state are achieved. Further drain control voltages are individually applied to drain terminals or source terminals of the FET in each switching circuit section, and a voltage according to an electric power value of the high frequency signal supplied to each of switching circuit sections is supplied as the gate control voltage and the drain control voltage.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.