US Patent 7178234 Method of manufacturing multi-layer printed circuit board
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Patent Inventor Names
Hiroaki Satake0
Tetsuya Tanabe0
Yogo Kawasaki0
Yutaka Iwata0
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Patent abstract
Through holes 36 are formed to penetrate a core substrate 30 and lower interlayer resin insulating layers 50, and via holes 66 are formed right on the through holes 36, respectively. Due to this, the through holes 36 and the via holes 66 are arranged linearly, thereby making it possible to shorten wiring length and to accelerate signal transmission speed. Also, since the through holes 36 and the via holes 66 to be connected to solder bumps 76 (conductive connection pins 78), respectively, are directly connected to one another, excellent reliability in connection is ensured.
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US Patent 07178234 Method of manufacturing multi-layer printed circuit board US Patent 7178234 Method of manufacturing multi-layer printed circuit board
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Patent Number
071782340
Patent Number
71782340
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Official Website
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Patent Jurisdiction
Patent Number
071782340
Date of Patent
February 20, 2007
0Patent Application Number
111066420
Date Filed
April 15, 2005
0Official Website
Patent Primary Examiner
Edits on 8 Jun, 2022
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US Patent 07178234 Method of manufacturing multi-layer printed circuit board
Infobox
Is a
Patent jurisdiction
Patent number
07178234
Date of patent
February 20, 2007
Patent application number
11106642
Date Filed
April 15, 2005
Patent primary examiner
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