US Patent 7208375 Semiconductor device

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Edits on 6 Sep, 2023

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edited on 6 Sep, 2023

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Patent Inventor Names

Hiroaki Shishido0

Kosuke Ohshima0

Mizue Kitada0

Shinji Kunori0

Toru Kurosaki0

Edits on 1 Sep, 2023

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edited on 1 Sep, 2023

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Patent abstract

A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.

Edits on 23 May, 2023

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edited on 23 May, 2023

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Official Website

https://pdfpiw.uspto.gov/.piw?Docid=07208375

Edits on 21 May, 2023

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Golden AI