US Patent 7217962 Wire mesh patterns for semiconductor devices
Patent 7217962 was granted and assigned to Transmeta on May, 2007 by the United States Patent and Trademark Office.
All edits
Edits on 6 Sep, 2023
Golden AI
Edits made to:
Infobox (+1 properties)
Infobox
Patent Inventor Names
Robert Paul Masleid0
Edits on 1 Sep, 2023
Golden AI
Edits made to:
Article (+413 characters)
Article
Patent abstract
Different patterns of interconnects for connecting wells in a semiconductor device are described. For example, a semiconductor device may include n-wells and p-wells arrayed in rows and columns that lie on a rectilinear grid. Electrically conductive interconnects link at least some of the wells. The interconnects are arranged as a mesh having openings that are substantially rectangular in shape.
Edits on 15 Jul, 2023
Golden AI
Edits made to:
Infobox (+1/-1 properties)
US Patent 07217962 Wire mesh patterns for semiconductor devices US Patent 7217962 Wire mesh patterns for semiconductor devices
Infobox
Patent Number
072179620
Patent Number
72179620
Edits on 22 May, 2023
Golden AI
Edits made to:
Infobox (-1 properties)
Infobox
Official Website
Edits on 23 Sep, 2022
Golden AI
Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
072179620
Date of Patent
May 15, 2007
0Patent Application Number
111716730
Date Filed
June 30, 2005
0Official Website
Patent Primary Examiner
Edits on 8 Jun, 2022
Golden AI
Edits made to:
Infobox (+1 properties)
Infobox
Website URL
Edits on 21 Nov, 2021
Golden AI
Edits made to:
Infobox (+8 properties)
US Patent 07217962 Wire mesh patterns for semiconductor devices
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07217962
Date of patent
May 15, 2007
Patent application number
11171673
Date Filed
June 30, 2005
Patent primary examiner
Find more entities like US Patent 7217962 Wire mesh patterns for semiconductor devices
Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
