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US Patent 7223653 Process for forming a buried plate

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
June 15, 2004
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Date of Patent
May 29, 2007
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Patent Application Number
10710045
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Patent Citations Received
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US Patent 12073082 High capacity memory circuit with low effective latency
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US Patent 11842777 Methods for reducing disturb errors by refreshing data alongside programming or erase operations
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US Patent 11915768 Memory circuit, system and method for rapid retrieval of data sets
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US Patent 11937424 Thin-film storage transistors in a 3-dimensional array of nor memory strings and process for fabricating the same
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US Patent 12002523 Memory circuit, system and method for rapid retrieval of data sets
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US Patent 11749344 Three-dimensional vertical nor flash thin-film transistor strings
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US Patent 11751388 3-dimensional nor strings with segmented shared source regions
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US Patent 11751391 Methods for fabricating a 3-dimensional memory structure of nor memory strings
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US Patent 11751392 Fabrication method for a 3-dimensional NOR memory array
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US Patent 11839086 3-dimensional memory string array of thin-film ferroelectric transistors
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•••
Patent Inventor Names
Ramachandra Divakaruni
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Kangguo Cheng
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
7223653
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Patent Primary Examiner
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William M. Brewster
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