US Patent 7251710 Cache memory subsystem including a fixed latency R/W pipeline

A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be configured to schedule reads and writes of information associated with the cache storage using a fixed latency pipeline. In response to scheduling a read request, the scheduler may be further configured to cause an associated write to occur a fixed number of cycles after the scheduling of the read request.