Patent attributes
An electronic device (60) including a first integrated circuit (IC) die (62) electrically connected to a first lead frame (64) and a second IC die (66) electrically connected to a second lead frame (68). The first lead frame (64) is electrically connected to the second lead frame (68) by at least one stud bump (72), which is selectively formed where an electrical connection between the first lead frame (64) and the second lead frame (68) is required. The first and second lead frames (64) and (68), the first and second IC dies (62) and (66), and the at least one stud bump (72) are encapsulated by a mold compound (74) to form a 3D package.