US Patent 7262987 SRAM cell using tunnel current loading devices

An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.