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US Patent 7269212 Low-latency equalization in multi-level, multi-line communication systems

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Is a
Patent
Patent
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Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
72692120
Patent Inventor Names
Haw-Jyh Liaw0
Jun Kim0
Jared L. Zerbe0
Pak Shing Chau0
Date of Patent
September 11, 2007
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Patent Application Number
096546430
Date Filed
September 5, 2000
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Patent Citations Received
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US Patent 11842986 Multi-chip module (MCM) with interface adapter circuitry
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US Patent 11855043 Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates
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US Patent 11855056 Low cost solution for 2.5D and 3D packaging using USR chiplets
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US Patent 11893242 Multi-chip module (MCM) with multi-port unified memory
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US Patent 11971820 Variable modulation scheme for memory device access or operation
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US Patent 11990912 Data transmission using delayed timing signals
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0
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Patent Primary Examiner
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Emmanuel Bayard
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Patent abstract

Low-latency equalization mechanisms for multi-PAM communication systems are disclosed that reduce delay and complexity in signal correction mechanisms. The equalization mechanisms tap into input signals for a multi-PAM signal driver, and compensate for attenuation along a signal transmission line, crosstalk between adjacent lines, and signal reflections due to impedance discontinuities along the line.

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