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US Patent 7269212 Low-latency equalization in multi-level, multi-line communication systems

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
September 5, 2000
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Date of Patent
September 11, 2007
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Patent Application Number
09654643
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Patent Citations Received
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US Patent 11842986 Multi-chip module (MCM) with interface adapter circuitry
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US Patent 11855043 Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates
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US Patent 11855056 Low cost solution for 2.5D and 3D packaging using USR chiplets
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US Patent 11893242 Multi-chip module (MCM) with multi-port unified memory
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US Patent 11971820 Variable modulation scheme for memory device access or operation
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US Patent 11990912 Data transmission using delayed timing signals
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US Patent 11706061 High speed signaling system with adaptive transmit pre-emphasis
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US Patent 11750426 Edge enhancement for signal transmitter
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US Patent 11756598 Electronic device for performing data alignment operation
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US Patent 11775460 Communicating data with stacked memory dies
•••
Patent Inventor Names
Haw-Jyh Liaw
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Jun Kim
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Jared L. Zerbe
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Pak Shing Chau
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
7269212
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Patent Primary Examiner
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Emmanuel Bayard
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