Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Mark A. Helm0
Roger W. Lindsay0
Date of Patent
September 25, 2007
0Patent Application Number
112094870
Date Filed
August 23, 2005
0Patent Primary Examiner
Patent abstract
A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first conductive layer formed on a substrate and coupled to source select gates associated with the two or more columns of serially-connected floating-gate transistors. The source line also includes a second conductive layer formed on the first conductive layer, where the second layer has a greater electrical conductivity than the first conductive layer.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.
