Patent attributes
Disclosed is an output buffer including a first output buffer for data for receiving a data signal and outputting an output signal from an output terminal, a second output buffer with an output end thereof connected to the output terminal, and a selection circuit. The selection circuit receives a control signal indicating whether de-emphasis enabled or de-emphasis is disabled and performs switching control so that when the control signal indicates that the de-emphasis is disabled, the second output buffer is deactivated, when the control signal indicates that the de-emphasis is enabled, emphasis data obtained on delaying the data signal through a delay circuit is supplied to an input end of the second output buffer, thereby causing the second output buffer to operate as a de-emphasis buffer, and when a test control signal is of a value indicating an amplitude margin test, the data signal is selected to be supplied to the input end of the second output buffer.
