US Patent 7349752 Dynamically coupled metrology and lithography
Patent 7349752 was granted and assigned to Integrated Device Technology on March, 2008 by the United States Patent and Trademark Office.
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Patent abstract
Methods for determining tolerances are disclosed that can be used for determining whether a lot of semiconductor wafers needs to be reworked. Overlay tolerance, critical dimension tolerance and a dynamic line edge placement tolerance are determined using error measurements that are taken from sample wafers in the lot, giving tolerances that reflect the error state of that particular lot of semiconductor wafers.
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US Patent 07349752 Dynamically coupled metrology and lithography US Patent 7349752 Dynamically coupled metrology and lithography
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Patent Number
0734975200
Patent Number
734975200
Edits on 24 Mar, 2023
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Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
073497520
Date of Patent
March 25, 2008
0Patent Application Number
107736650
Date Filed
February 6, 2004
0Official Website
Patent Primary Examiner
Edits on 23 Sep, 2022
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Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
073497520
Date of Patent
March 25, 2008
0Patent Application Number
107736650
Date Filed
February 6, 2004
0Official Website
Patent Primary Examiner
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US Patent 07349752 Dynamically coupled metrology and lithography
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07349752
Date of patent
March 25, 2008
Patent application number
10773665
Date Filed
February 6, 2004
Patent primary examiner
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