Is a
Patent attributes
Patent Jurisdiction
Patent Number
Date of Patent
May 13, 2008
Patent Application Number
11318433
Date Filed
December 28, 2005
Patent Primary Examiner
Patent abstract
A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The method includes forming a shallow trench in a silicon substrate.
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