US Patent 7371655 Method of fabricating low-power CMOS device
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Patent abstract
A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The method includes forming a shallow trench in a silicon substrate.
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US Patent 07371655 Method of fabricating low-power CMOS device US Patent 7371655 Method of fabricating low-power CMOS device
Infobox
Patent Number
0737165500
Patent Number
737165500
Edits on 4 Apr, 2023
Golden AI
Infobox
Is a
Patent Jurisdiction
Patent Number
073716550
Date of Patent
May 13, 2008
0Patent Application Number
113184330
Date Filed
December 28, 2005
0Official Website
Patent Primary Examiner
Edits on 23 Sep, 2022
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Infobox
Is a
Patent Jurisdiction
Patent Number
073716550
Date of Patent
May 13, 2008
0Patent Application Number
113184330
Date Filed
December 28, 2005
0Official Website
Patent Primary Examiner
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US Patent 07371655 Method of fabricating low-power CMOS device
Infobox
Is a
Patent jurisdiction
Patent number
07371655
Date of patent
May 13, 2008
Patent application number
11318433
Date Filed
December 28, 2005
Patent primary examiner
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