Patent attributes
Automatic fault recovery of upsets in a memory controller are provided to minimize data loss. In addition to memory control, the present invention allows for the incorporation of majority voting circuits with integrated alignment between three voted data streams. The memory array is divided into two basic components: (1) the write side (data in); and (2) the read side (data out). Each of these components has a separate memory address counter. The write counter is loaded into a holding register during a synchronization period. After determining the validity of the write cycle for fault tolerance and setting data latency for pipelining, the read counter is loaded with the write counter value. The reading of the memory array commences at the counter value that was stored in the read counter, which is the same as the original write counter value.
