US Patent 7417329 System-in-package structure
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Patent Inventor Names
Cheng-Yin Lee0
Chi-Chih Chu0
Meng-Jung Chuang0
Wei-Chang Tai0
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Patent abstract
A system-in-package structure includes a carrier substrate having a molding area and a periphery area, at least a chip disposed in the molding area, an encapsulation covering the chip and the molding area, a plurality of solder pads disposed in the periphery area, and a solder mask disposed in the periphery area and partially exposing the surface of the solder pads. The solder mask includes at least a void therein.
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US Patent 07417329 System-in-package structure US Patent 7417329 System-in-package structure
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Patent Number
074173290
Patent Number
74173290
Edits on 30 Mar, 2023
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Patent Jurisdiction
Patent Number
074173290
Date of Patent
August 26, 2008
0Patent Application Number
114202300
Date Filed
May 25, 2006
0Official Website
Patent Primary Examiner
Edits on 9 Jun, 2022
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US Patent 07417329 System-in-package structure
Infobox
Is a
Patent jurisdiction
Patent number
07417329
Date of patent
August 26, 2008
Patent application number
11420230
Date Filed
May 25, 2006
Patent primary examiner
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