US Patent 7425489 Self-aligned shallow trench isolation
Patent 7425489 was granted and assigned to Cypress Semiconductor Corporation on September, 2008 by the United States Patent and Trademark Office.
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Patent Inventor Names
Geethakrishnan Narasimhan0
Saurabh D. Chowdhury0
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Patent abstract
A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer.
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US Patent 07425489 Self-aligned shallow trench isolation US Patent 7425489 Self-aligned shallow trench isolation
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Patent Number
074254890
Patent Number
74254890
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Official Website
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Is a
Current Assignee
0
Patent Jurisdiction
Patent Number
074254890
Date of Patent
September 16, 2008
0Patent Application Number
112824220
Date Filed
November 18, 2005
0Official Website
Patent Primary Examiner
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US Patent 07425489 Self-aligned shallow trench isolation
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07425489
Date of patent
September 16, 2008
Patent application number
11282422
Date Filed
November 18, 2005
Patent primary examiner
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