Patent attributes
A ferroelectric RAM (Random Access Memory) device includes at least one memory cell constructed of one access transistor operating by a word line enable signal, and one ferroelectric capacitor connected between a bit line and the access transistor. The device has a cell array structure based on a repeated array of the memory cells. The device also includes a word line driver suitable for a high integration and reducing power consumption. The driving method in the ferroelectric RAM device generates a word line enable signal having a level of power source voltage, to read and write data. The method has advantages of being suitable for a high integration, enhancing an operating speed and reducing power consumption and providing stabilized read and write operations.
