Patent attributes
An integrated circuit (IC) having an electrostatic discharge (ESD) protection circuit therein is provided. The IC comprises a plurality of bonding pads, a plurality of ESD units, a first ESD bus and a second ESD bus. The first ESD bus has no direct connection with any power pad of the IC. Each ESD unit comprises a first diode, a second diode and an ESD clamping device. Due to the one-to-one correspondent of each bonding pad with an ESD unit, the present invention ensures ESD continuity through a continuous charge dissipation path no matter what kind of pin-to-pin ESD test the IC is undergoing or how many power sources the IC has. In addition, a bonding pad over active circuitry (BOAC) structure can also be deployed in the present invention to provide a better ESD protection for the whole IC chip.
