US Patent 7470973 Semiconductor device and semiconductor integrated circuit device
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Patent Inventor Names
Yoshihiro Takao0
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Patent abstract
In each of a p-channel MOS transistor and an n-channel MOS transistor, a channel direction is set in the <100> direction and a first stressor film accumulating therein a tensile stress is formed in a STI device isolation structure. Further, a second stressor film accumulating therein a tensile stress is formed on a silicon substrate so as to cover the device isolation structure.
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US Patent 07470973 Semiconductor device and semiconductor integrated circuit device US Patent 7470973 Semiconductor device and semiconductor integrated circuit device
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Patent Number
074709730
Patent Number
74709730
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Patent Jurisdiction
Patent Number
074709730
Date of Patent
December 30, 2008
0Patent Application Number
114118880
Date Filed
April 27, 2006
0Official Website
Patent Primary Examiner
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US Patent 07470973 Semiconductor device and semiconductor integrated circuit device
Infobox
Is a
Patent jurisdiction
Patent number
07470973
Date of patent
December 30, 2008
Patent application number
11411888
Date Filed
April 27, 2006
Patent primary examiner
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