Patent attributes
A semiconductor memory having a plurality of static random access memory cells, word lines, first and second bit lines orthogonal to the word lines, and threshold voltage control lines parallel to the word lines and each of the static random access memory cell includes the first and the second driver transistors, the first and the second load transistors, and the first and the second transfer transistors configured by Fin field effect transistors, and at least one of the Fin field effect transistors is configured by a separated-gate type double-gate field effect transistor comprising a first gate electrode and a second gate electrode and controlling a voltage for the first gate electrode to form a channel, and controlling a voltage for the second gate electrode to decrease a threshold voltage at the time of writing data.
