US Patent 7565638 Density-based layer filler for integrated circuit design

A system and method for performing density-based layer filling on a design layout encoding of an integrated circuit device is disclosed. In some embodiments, the density-based layer filler may identify open areas on a given design layer in which one or more minimum density rules are not met and may insert dummy shapes only in those identified areas. The dummy shapes may be constructed so as not to violate one or more other design rules. The density-based layer filler may access a configuration file comprising layer density rules and other design rules and may generate a run deck dependent on the contents of the configuration file. The density-based layer filler may be applied iteratively to a design in checking windows of various sizes according to multiple window sizes and step values specified in the configuration file. The dummy shapes may be electrically connected to an existing ground wire after insertion.