US Patent 7576434 Wafer-level solder bumps

In one embodiment, the present invention includes a semiconductor package having a support substrate coupled to a first semiconductor die, where the first semiconductor die includes first conductive bumps, and a second semiconductor die includes second conductive bumps, and where the first and second die are coupled by joints formed of the first and second conductive bumps and a solder material therebetween. Other embodiments are described and claimed.