US Patent 7584392 Test compaction using linear-matrix driven scan chains

Patent 7584392 was granted and assigned to Cadence Design Systems on September, 2009 by the United States Patent and Trademark Office.

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Patent

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Current Assignee

Cadence Design Systems

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

7584392

Date of Patent

September 1, 2009

Patent Application Number

10630537

Date Filed

July 29, 2003

Patent Primary Examiner

‌

Phung M Chung

Patent abstract

A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.

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