Patent 7584392 was granted and assigned to Cadence Design Systems on September, 2009 by the United States Patent and Trademark Office.
A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.