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US Patent 7635987 Configuring circuitry in a parallel processing environment

Patent 7635987 was granted and assigned to Massachusetts Institute of Technology on December, 2009 by the United States Patent and Trademark Office.

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Is a
Patent
Patent

Patent attributes

Current Assignee
Massachusetts Institute of Technology
Massachusetts Institute of Technology
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7635987
Patent Inventor Names
Anant Agarwal0
Date of Patent
December 22, 2009
Patent Application Number
11302983
Date Filed
December 13, 2005
Patent Citations Received
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US Patent 12106099 Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric
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US Patent 11886377 Reconfigurable arithmetic engine circuit
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US Patent 11907157 Reconfigurable processor circuit architecture
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US Patent 11915057 Computational partition for a multi-threaded, self-scheduling reconfigurable computing fabric
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US Patent 11977509 Reconfigurable processor circuit architecture
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US Patent 11868163 Efficient loop execution for a multi-threaded, self-scheduling reconfigurable computing fabric
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US Patent 11880687 System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network
0
Patent Primary Examiner
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Anh Q Tran
Patent abstract

An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and reconfigurable logic that includes one or more connections to the switch.

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