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US Patent 7635987 Configuring circuitry in a parallel processing environment

Patent 7635987 was granted and assigned to Massachusetts Institute of Technology on December, 2009 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
Current Assignee
Massachusetts Institute of Technology
Massachusetts Institute of Technology
Date Filed
December 13, 2005
Date of Patent
December 22, 2009
Patent Application Number
11302983
Patent Citations Received
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US Patent 12106099 Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric
0
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US Patent 11886377 Reconfigurable arithmetic engine circuit
0
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US Patent 11907157 Reconfigurable processor circuit architecture
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US Patent 11915057 Computational partition for a multi-threaded, self-scheduling reconfigurable computing fabric
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US Patent 11977509 Reconfigurable processor circuit architecture
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US Patent 11868163 Efficient loop execution for a multi-threaded, self-scheduling reconfigurable computing fabric
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US Patent 11880687 System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network
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Patent Inventor Names
Anant Agarwal
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7635987
Patent Primary Examiner
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Anh Q Tran

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