Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
April 27, 2010
Patent Application Number
11324455
Date Filed
January 3, 2006
Patent Primary Examiner
Patent abstract
In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as desired.
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