US Patent 7774726 Dummy fill for integrated circuits
Patent 7774726 was granted and assigned to Cadence Design Systems on August, 2010 by the United States Patent and Trademark Office.
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Methods and systems for correcting inter-level variations are disclosed. One approach addresses thickness and/or topological variations based upon layers in an IC design that do not allow the placement of dummy fill, in which dummy fill is added to certain layers of the IC to reduce process variations caused by other layers in the semiconductor devices. To accomplish this, layers in the design that cannot accommodate dummy fill are modeled to determine their topological variations. Other layers that are capable of receiving dummy fill are then analyzed to receive the correct quantity and distribution of dummy fill to correct for the topological variations from the non-dummy fill layers.
US Patent 07774726 Dummy fill for integrated circuits US Patent 7774726 Dummy fill for integrated circuits
US Patent 07774726 Dummy fill for integrated circuits
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