US Patent 7779314 System and related method for chip I/O test
All edits
Edits on 31 Oct, 2023
Golden AI
Edits made to:
Article (+400 characters)
Article
Patent abstract
System and related method for testing a chip with a high-speed bus interface in a low speed testing environment is provided. The testing method for testing input/output functions of a chip includes: establishing an inner loop path between a transmission mechanism and a receiving mechanism of the chip; transmitting a testing data; and receive the testing data via the inner loop path.
Edits on 16 Jul, 2023
Golden AI
Edits made to:
Infobox (+1/-1 properties)
US Patent 07779314 System and related method for chip I/O test US Patent 7779314 System and related method for chip I/O test
Infobox
Patent Number
0777931400
Patent Number
777931400
Edits on 21 May, 2023
Golden AI
Edits made to:
Infobox (-1 properties)
Infobox
Official Website
Edits on 24 Mar, 2023
Golden AI
Infobox
Is a
Patent Jurisdiction
Patent Number
077793140
Date of Patent
August 17, 2010
0Patent Application Number
116160010
Date Filed
December 25, 2006
0Official Website
Patent Primary Examiner
Edits on 23 Sep, 2022
Golden AI
Infobox
Is a
Patent Jurisdiction
Patent Number
077793140
Date of Patent
August 17, 2010
0Patent Application Number
116160010
Date Filed
December 25, 2006
0Official Website
Patent Primary Examiner
Edits on 3 Jun, 2022
Golden AI
Edits made to:
Infobox (+1 properties)
Infobox
Website URL
Edits on 5 Dec, 2021
Golden AI
Edits made to:
Infobox (+7 properties)
US Patent 07779314 System and related method for chip I/O test
Infobox
Is a
Patent jurisdiction
Patent number
07779314
Date of patent
August 17, 2010
Patent application number
11616001
Date Filed
December 25, 2006
Patent primary examiner
Find more entities like US Patent 7779314 System and related method for chip I/O test
Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
