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US Patent 7791922 Semiconductor memory device

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
August 5, 2008
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Date of Patent
September 7, 2010
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Patent Application Number
12186088
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Patent Citations Received
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US Patent 12108609 Memory bit-cell with stacked and folded planar capacitors
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US Patent 11997853 1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset
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US Patent 12062584 Iterative method of multilayer stack development for device applications
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US Patent 12087730 Multi-input threshold gate having stacked and folded planar capacitors with and without offset
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US Patent 12094511 Write disturb mitigation for column multiplexed non-linear polar material based multi-capacitor bit-cell
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US Patent 12096638 One transistor and N memory element based memory bit-cell having stacked and folded planar memory elements with and without offset
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US Patent 11751403 Common mode compensation for 2T1C non-linear polar material based memory bit-cell
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US Patent 11758708 Stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell
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US Patent 11765908 Memory device fabrication through wafer bonding
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US Patent 11770936 Stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell
•••
Patent Inventor Names
Sumiko Doumae
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Daisaburo Takashima
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
7791922
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Patent Primary Examiner
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Michael T. Tran
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