Patent attributes
The integrated circuit devices disclosed herein generally include two semiconductor dies. The first die generally has little or no I/O or ESD protection and includes a first plurality of exposed terminals (e.g., bump pads). The second die generally includes (i) a second plurality of exposed terminals, wherein at least one of the second plurality of terminals is in electrical communication with one or more of the first plurality of terminals, (ii) a plurality of input and/or output (I/O) circuits, wherein at least one of the I/O circuits is in electrical communication with one or more of the second plurality of terminals, and (iii) a plurality of I/O terminals, wherein at least one of the I/O terminals is in electrical communication with one or more of the I/O circuits. The present invention advantageously provides the ability to fabricate the second die using different (e.g., less expensive) manufacturing processes than those used to fabricate the first die.
