US Patent 7839196 Multi-phase clock generation circuit having a low skew imprecision

A multi-phase clock generation circuit having a low skew imprecision is presented. The circuit includes a phase clock generation block and a phase correction block. The phase clock generation block is configured to generate a plurality of phase clocks having phases different from each other with response to a pair of input clocks. The phase correction block is configured to generate final output interpolated phase clocks in which each has a center phase by adjusted by multiple phase clocks that have adjacent phases.