US Patent 7865851 Capacitance extraction of intergrated circuits with floating fill

Patent 7865851 was granted and assigned to Mentor Graphics on January, 2011 by the United States Patent and Trademark Office.

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Patent

Patent attributes

Current Assignee

Mentor Graphics

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

7865851

Patent Inventor Names

David J. Gurney0

Date of Patent

January 4, 2011

Patent Application Number

11369565

Date Filed

March 6, 2006

Patent Primary Examiner

‌

Helen Rossoshek

Patent abstract

The present invention improves the accuracy of parasitic capacitance extraction of IC designs with floating fill. One embodiment of the present invention approximates the coupling capacitances of fill nets beyond an exact-approximation level by a fill net elimination method whereby actual capacitances of the fill net to the variable level are fully extracted and remaining capacitances are approximated.

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