US Patent 7865851 Capacitance extraction of intergrated circuits with floating fill
Patent 7865851 was granted and assigned to Mentor Graphics on January, 2011 by the United States Patent and Trademark Office.
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Patent abstract
The present invention improves the accuracy of parasitic capacitance extraction of IC designs with floating fill. One embodiment of the present invention approximates the coupling capacitances of fill nets beyond an exact-approximation level by a fill net elimination method whereby actual capacitances of the fill net to the variable level are fully extracted and remaining capacitances are approximated.
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Patent Inventor Names
David J. Gurney0
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US Patent 07865851 Capacitance extraction of intergrated circuits with floating fill US Patent 7865851 Capacitance extraction of intergrated circuits with floating fill
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Patent Number
07865851
Patent Number
7865851
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US Patent 07865851 Capacitance extraction of intergrated circuits with floating fill
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Is a
Current assignee
Patent jurisdiction
Patent number
07865851
Date of patent
January 4, 2011
Patent application number
11369565
Date Filed
March 6, 2006
Patent primary examiner
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