US Patent 7867817 Method for manufacturing a wafer level package
Patent 7867817 was granted and assigned to Qimonda on January, 2011 by the United States Patent and Trademark Office.
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Patent abstract
A method for manufacturing a wafer level package of an integrated circuit element for direct attachment to a wiring board is disclosed. An integrated circuit element includes input/output pads located on an active side. A non-conductive support structure is formed on the active side of the integrated circuit element in an area that is free from input/output pads. A conductive path is formed upon the support structure and a non-conductive coating is formed on over the active side of the integrated circuit element such that a surface is formed which leaves interface pads accessible.
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Patent Inventor Names
Harry Hedler0
Henning Mieth0
Stephan Dobritz0
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US Patent 07867817 Method for manufacturing a wafer level package US Patent 7867817 Method for manufacturing a wafer level package
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Patent Number
078678170
Patent Number
78678170
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Official Website
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Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
078678170
Date of Patent
January 11, 2011
0Patent Application Number
120238530
Date Filed
January 31, 2008
0Official Website
Patent Primary Examiner
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US Patent 07867817 Method for manufacturing a wafer level package
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07867817
Date of patent
January 11, 2011
Patent application number
12023853
Date Filed
January 31, 2008
Patent primary examiner
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