US Patent 7925941 Test compaction using linear-matrix driven scan chains
Patent 7925941 was granted and assigned to Cadence Design Systems on April, 2011 by the United States Patent and Trademark Office.
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Patent abstract
A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.
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Patent Inventor Names
Sandeep Bhatia0
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US Patent 07925941 Test compaction using linear-matrix driven scan chains US Patent 7925941 Test compaction using linear-matrix driven scan chains
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Patent Number
079259410
Patent Number
79259410
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Patent Jurisdiction
Patent Number
079259410
Date of Patent
April 12, 2011
0Patent Application Number
125499510
Date Filed
August 28, 2009
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US Patent 07925941 Test compaction using linear-matrix driven scan chains
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Is a
Current assignee
Patent jurisdiction
Patent number
07925941
Date of patent
April 12, 2011
Patent application number
12549951
Date Filed
August 28, 2009
Patent primary examiner
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